1. Field of the Invention
The present invention relates to the field of integrated circuit frequency dividers, particularly the realization of a symmetrical and fully programmable frequency divider using a high speed linear feedback shift register (LFSR).
2. Background of the Invention
In its most basic implementation, a divider circuit will accept an input signal with a given frequency and provide an output signal with a lower frequency. The relationship between the output and input signal frequencies is of the form of a programmable ratio, that is, the frequency of the output signal will be the frequency of the input signal divided by a factor N. This factor, known as the ‘divide value’ of the divider circuit, is programmable via input ‘control’ signals to the divider. These control signals are digital in nature, can assume values of ‘1’ or ‘0’, and the number of control signals will determine the number of ‘divide modes’ of the divider, that is, the number of possible values for N. The other key characteristics of divider circuits are the ‘divide range’ and ‘divide resolution’. The ‘divide range’ is the maximum and minimum value of N, and the ‘divide resolution’ is the granularity of N, that is, the difference between consecutive N values. For example a divider with two control bits can generally have 22=4 divide modes. If the divide modes have N values of 2, 4, 6, 8, then the divide range is 2 through 8, and the divide resolution is 2.
The performance requirements of divider circuits have increasingly demanded a greater number of divide modes, a wider divide range, and the smallest possible divide resolution. There are currently many divider styles in use that address each of these requirements individually. The real challenge, however, is to meet all of these requirements along with the additional demands that a divider circuit be able to process higher signal frequencies, occupy less physical area and consume less power.
The LFSR is increasingly utilized as a primary element in frequency divider circuits. Essentially a counter, the LFSR can operate at much higher frequencies than traditional counter designs due its simplicity of design. The LFSR typically consumes less power and area than conventional counter designs as well.
The core element of a conventional frequency divider circuit is a counter. A counter is a circuit generally composed of multiple storage elements, such as latches. The value of the storage elements, or latches, at any given time defines the ‘state’ of the counter. The counter is designed such that it will change its state in response to a triggering event. With latches, this event is usually a rising or falling clock transition. The total number of unique states the counter will occupy while being clocked determines the maximum count it can achieve. Once the counter has reaches its maximum count, it may stop counting and await a ‘refresh’ signal, or it may repeat the counting cycle. Most counters perform the latter and will continuously cycle through a set of unique states. This sequence is periodic in nature and is the basis for frequency division. In a frequency divider circuit, an output signal is generated such that it will complete one cycle for each iteration of the counter through the set of unique states. If the number of unique states is N, then the divisor value of the divider is N and the frequency of the output signal is equivalent to the frequency of the counter input clock signal divided by N.
Key features of most counters includes not only the number of unique states but also the manner in which the counter cycles through each state. The state of a counter can be represented as a binary number, where each latch represents a single ‘bit’. As clock transitions occur, the state of the counter usually changes such that the binary number corresponding to a particular state either increases or decreases in a sequential manner. FIG. 1 shows a state transition table 100 for a four latch counter, wherein the columns L0–L3 represent the latches, or bits that define the state. In FIG. 2, the logic schematic of the four latch binary sequential counter frequency divider 101 is shown. The most significant bit (MSB) of the counter serves as the output OUT, which will complete one cycle for each iteration of the counter through the set of unique states. A major disadvantage of the sequential counter approach is that it requires progressively more complex logic between each stage as the counter grows in size, which will cause the performance of the divider to degrade.
A class of dividers designed to overcome the limitations of the sequential counter divider circuit is the binary shift register based frequency divider 102 shown in FIG. 3. In this design, the output of the shift-register is inverted and fed back to the input, providing greater economy with respect to the logic required between stages. However, the shift-register divider will transition through only one of two unique state domains as depicted in the dual state transition table 103 of FIG. 4. Consequently, only one half of the total number of available states of the divider are useable. In addition, the shift-register divider requires initialization of the latches to prevent spurious state transitions between the two domains of the state transition table. Thus, while the shift-register divider addresses the performance issues of the counter based designs, it does so at the expense of the maximum divisor value.
FIG. 5 illustrates a linear feedback shift register (LFSR) 104 implementation of a frequency divider. This type of design allows the divider to cycle through all but one of its unique states, while enjoying low circuit overhead in the data path. One drawback, however, is that the states do not transition in a predictable order which prevents the output from being taken directly from one of the latches. Instead, an additional logic gate, such as the AND gate 105 shown in FIG. 5 is needed to detect the occurrence of one of the states. The additional circuitry slightly limits the performance of the divider because of the added loading but ensures transition through all of the unique states. While the amount of logic placed within the datapath of the divider is minimal for the LFSR, this design will not produce an output with a fifty percent duty cycle. The output of the LFSR divider has a pulse width equal to one period of the input clock. The state transition table 106 for the LFSR divider is shown in FIG. 6.
FIG. 8 shows a prior art programmable LFSR disclosed in U.S. Pat. No. 6,057,719 issued to Austin, et al., which is incorporated herein by reference.